A linear voltage regulator is often used for providing stepped down power to electronic devices, particularly devices having low power or low noise requirements. The linear voltage regulator is easy to use and inexpensive to implement. However, it is extremely inefficient since the difference between a higher input voltage and a lower output voltage is dissipated as heat.
A low dropout regulator (“LDO”) is a linear voltage regulator that operates with input voltage only slightly higher than the output voltage, and therefore is somewhat more efficient than a standard linear voltage regulator. The LDO regulator is particularly well-suited for low voltage applications. However, the load demand on a LDO regulator can change quickly, resulting in a temporary glitch on the output voltage. Most digital circuits do not react favorably to large voltage transients, and it would be desirable to avoid this issue.
A simplified block diagram of a typical LDO linear voltage regulator 100 is shown in FIG. 1. A pass element 130 takes an input voltage VIN and provides an output voltage VOUT under the control of an error amplifier 110. The output voltage VOUT is sampled as a feedback voltage signal VFB through a resistive divider R1, R2 in the output stage 140, and the feedback voltage signal VFB is coupled to the inverting input of the error amplifier 110. The non-inverting input of the error amplifier 110 is coupled to a reference voltage VREF, which is usually derived from an internal bandgap reference 101. The error amplifier 110 compares the voltages at its inputs and operates to try and force the input voltages to be equal by sourcing current as required to meet the demand for load current by charging the output capacitor COUT.
At start up, the error amplifier 110 senses that the output voltage VOUT is low, and the pass element 130 is driven as hard as possible to meet the load requirement. The pass element 130 therefore pulls a large in-rush current to charge the output capacitance COUT, which is undesirable.
One solution to this problem is to employ a soft start circuit in the linear regulator to limit the initial power demand and thereby limit the current requirements at start up or turn on. However, such circuits cannot be readily optimized to provide a fast turn on of the system. Further, incorporating a current limiting circuit into a fast regulating LDO is a challenge because there are multiple feedback loops and making all loops stable can become challenging. Current limiting becomes even more critical if the LDO has an external capacitor since the capacitor requires limiting the in-rush current when the LDO is turned on.
Thus, it would be desirable to find an effective alternative current limiting solution for a multi loop LDO which can handle fast load transient while still regulating the LDO and providing protection from in-rush current and other excessive current demands.